The Source-Gated Transistor Web Page

This page is dedicated to the Source-Gated Transistor concept. It is solely for educational purposes.

Source-gated transistors are unipolar field effect transistors (FET). However when the acronym FET or TFT is used without qualification it implies a field effect transistor in which the conductance of a channel between a source and a drain is affected by the gate potential, as in a MISFET or JFET. (B5, B6)

The SGT is very different from these FET devices both structurally and functionally because firstly the gate lies above or below the source so that the minimum separation between the gate and the source is at least the combined thickness of the insulating layer and the semiconductor (see Fig below) and secondly, transistor action occurs by the action of the gate field on a source barrier. A combination of these two features leads to a very low saturation voltage and very high output impedance. Furthermore, since the structure and operational principles are different from a standard FET there are advantages in the context of technology and electrical stability particularly in relation to poor quality semiconductors for thin film electronics.
The organisation of this website is aimed at summarising the features and scope of the SGT in the context of work carried out at the University of Surrey.
       Journal Publications are numbered J1, J2, ...etc.
       Conference Presentations are numbered C1, C2, ...etc.
       Unpublished works are numbered U1, U2, ...etc.
       Background works are numbered B1, B2, ...etc.
             Dr. F. Balon.


Fig.1 Showing the elemental SGT structure


Research Fellowship
Dr. Radu Sporea has been awarded a five-year Academic Research Fellowship by the Royal Academy of Engineering. The Fellowship is held at the University of Surrey and the work focuses on energy-efficient and high gain electronic circuits based on the Soruce-Gated Transistor.

About SGT

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